Verilog Blocking and Non Blocking

七人表决器，当有四人或四人以上的人同意是，表决通过。每个裁判控制一个开关，高电平表同意，在quartusII上用全加器来实现，当表决通过时，实验箱上的LED灯亮

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.

ＦＰＧＡ在通信上的运用：基于VHDL的帧同步程序(Application of FPGA in communication: Based on VHDL frame synchronization procedures )

布尔乘法器带testbench好用的工程啊(Boolean multiplier works with testbench nice ah)

VHDL code of a counter Code VHDL d un compteur

vhdl code for 8051 processor

实现扰码的功能，主要为64位在pcs子层传输的扰码器设计(To achieve the functions of scrambling code)

基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。(Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.)

just division the clock into 2