数字频率计 FPGA 用verilog语言编写

说明：  fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated

基于FPGA的PWM波生成程序，用于控制步进电机。(A PWM wave generater for driving stepper motor.)

在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)

离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.

这个文件中是UltraEdit的一些格式化文件说明 由于原来的 UltraEdit 不支持 HDL 语言的格式化显示，把文件解压得到的 wordfile.txt替换其安装目录下的 wordfile.txt 文件即可-This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its installation directory under the document can wordfile.txt

This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.

This is a divider, which is depicted as well. It is a programming language Vhdl.

vhdl 键盘程序，对键盘输入的字符进行判断，写入fpga中-VHDL key

ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)