Decimal precision counts, classic written, easy learning and reference for all t...

一个基于FPGA用verilogHDL设计的bayer格式转RGB格式的模块，本人设计(a code used for bayer_3RGB_interpolation ,which based on FPGA by verilogHDL)

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

一个开源mips处理器verilog 源码(wishbone interface wishbone interface)

VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。 本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。 经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。 (VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware description language VHDL system means a description of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u)

说明：  mojo v3 complete eagle schematic

FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)

ALTERA PCIE FPGA开发板（EP4C平台）DDR2内存测试代码(ALTERA PCIE FPGA development board (EP4C platform) DDR2 memory test code)

gps C/A码生成 生成gps32颗卫星伪码，方便，经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)

用于单片机的adc采集实验，经过降噪处理，结果精确(ADC acquisition experiment for single chip computer, after noise reduction processing, the result is accurate)

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)