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VHDL 基础语法篇

于 2020-06-20 发布 文件大小:73KB
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  VHDL 基础语法篇 —— VHDL VHDL硬件描述语言 1.1 VHDL概述 1.1.1 VHDL的特点 VHDL语言作为一种标准的硬件描述语言,具有结构严谨、描述能力强的特点,由于 VHDL语言来源于C、Fortran等计算机高级语言,在VHDL语言中保留了部分高级语言的原 语句,如if语句、子程序和函数等,便于阅读和应用。具体特点如下: 1. 支持从系统级到门级电路的描述,既支持自底向上(bottom-up)的设计也支持从顶向下 (top-down)的设计,同时也支持结构、行为和数据流三种形式的混合描述。 2. VHDL的设计单元的基本组成部分是实体(entity)和结构体(architecture),实体包含设 计系统单元的输入和输出端口信息,结构体描述设计单元的组成和行为,便于各模块之间数 据传送。利用单元(componet)、块(block)、过程(procure)和函数(function)等语句, 用结构化层次化的描述方法,使复杂电路的设计更加简便。采用包的概念,便于标准设计文 档资料的保存和广泛使用。(VHDL Basic Grammar Paper)

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VHDL 基础语法篇.doc, 304640 , 2019-07-01

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