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12
说明: 用FPGA进行等精度频率和相位差测量的程序,本程序是在EPEC6Q240C8下的程序(Carried out with the FPGA such as the frequency and phase measurement precision of the procedure, this procedure was the procedure under the EPEC6Q240C8)
- 2010-03-03 17:42:11下载
- 积分:1
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binary_adder_subtractor
binary adder / subtracter in vhdl
- 2012-12-10 14:54:57下载
- 积分:1
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Three-phase-power
利用FPGA,产生三相SPWM波,与后继硬件电路配合,形成三相电源。高效,实用。(Using FPGA, produce three-phase SPWM wave, with subsequent hardware circuit with the formation of three-phase power. Efficient and practical.)
- 2021-04-06 23:49:02下载
- 积分:1
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verilog-lfsr-master
说明: Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分:1
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ref-sdr-sdram-verilog
sdram控制器的开发程序,还有文档,可以参考以下(SDRAM controller development process, there is a document, you can refer to the following)
- 2008-06-13 22:15:41下载
- 积分:1
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这是一个基本的ARM7_Core
有基本功能 但不是太完善
这是一个基本的ARM7_Core
有基本功能 但不是太完善-This is a basic ARM7_Core has the basic functions, but not too perfect
- 2022-01-26 06:35:06下载
- 积分:1
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cfo_correction
说明: OFDM载波同步,Verilog编写,完全正确!!!(verilog )
- 2020-11-05 21:39:50下载
- 积分:1
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alarm
闹钟设计,VHDL,源代码。闹钟设计,VHDL,源代码。(Alarm clock design, VHDL, the source code.)
- 2011-05-23 18:30:29下载
- 积分:1
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黄金时段介绍STA
PrimeTime Intro to STA
-PrimeTime Intro to STA
- 2022-12-10 13:05:05下载
- 积分:1
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or2a
使用vhdl语言设计一位全加器,在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分:1