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percent
verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)
- 2005-03-08 21:33:38下载
- 积分:1
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2018全国大学生FPGA大赛封闭测试上机题
说明: 2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目,以及自己编写的verilog和testbench,欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)
- 2020-11-23 22:39:33下载
- 积分:1
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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器,并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
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- 2013-09-05 20:04:36下载
- 积分:1
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Reed-Solomon-RS-ENCODE-DECODE
支持GF(2^n)域的rs编解码,可直接修改参数实现不同方式的RS编码和解码(This program is an encoder/decoder for Reed-Solomon codes.)
- 2020-12-31 09:48:58下载
- 积分:1
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AD_100k
说明: ADC Reference code!Clock 100kHz
- 2020-06-24 10:40:02下载
- 积分:1
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Electronicorgan
利用VHDL编写的电子琴发生器,以简单的演奏电路论文(Electronic organ prepared using VHDL generator to perform a simple circuit Papers)
- 2009-03-06 08:52:10下载
- 积分:1
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系数为4的扰码生成器,并每四位扰码产生一个触发串并转换的触发信号,可用于4b/5b编码的触发信号。verilog程序,带test程序...
系数为4的扰码生成器,并每四位扰码产生一个触发串并转换的触发信号,可用于4b/5b编码的触发信号。verilog程序,带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
- 2022-08-08 00:04:21下载
- 积分:1
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histogram_new
Verilog语言描述,统计图片的像素值直方图(Verilog,Pictures of the pixel value histogram statistics)
- 2021-03-04 17:39:31下载
- 积分:1
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disptest
模拟示波器的现实程序,有x,y和光标。采用AD5440输出,现实效果很好。(示波器x-y方式)(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))
- 2013-09-13 23:18:19下载
- 积分:1
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rotary
Spartan 3E上的Rotary encoder控制程序,及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)
- 2010-11-27 01:40:13下载
- 积分:1