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本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。
this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-06-27 01:31:46下载
- 积分:1
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1553B总线接口技术研究及FPGA实现
基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)
- 2019-04-18 11:02:52下载
- 积分:1
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Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
- 2023-04-29 07:25:03下载
- 积分:1
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frequency divider
说明: FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1
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VHDL语言设计;功能描述:键盘扫描,不包含去抖电路
VHDL语言设计;功能描述:键盘扫描,不包含去抖电路-VHDL language design Function description: the keyboard scanning, does not contain a circuit debounced
- 2022-08-26 08:21:49下载
- 积分:1
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ise
xilinx的时序约束实验,通过阅读本文档,你可以用全局时序约束来轻松提高已有的项目的系统时钟频率,同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分:1
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HDLC接口协议的FPGA实现使用verilog
HDLC接口协议的FPGA实现使用verilog-design of HDLC
- 2022-06-02 20:47:21下载
- 积分:1
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cnt60
60进制计数器,(由一六进制和十进制连线组成)(60 binary counter (hexadecimal and decimal by a connection form))
- 2011-11-29 10:48:37下载
- 积分:1
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verilog例子资源,对于初学者很有帮助。
verilog例子资源,对于初学者很有帮助。-verilog examples of resources are very useful for beginners.
- 2023-08-15 15:30:03下载
- 积分:1
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calibration
CS5460校准程序,控制器为C8051F310,SPI通信协议,可以作为电表芯片示例(CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample)
- 2011-08-05 00:42:09下载
- 积分:1