利用扫描加记数程序实现百进制,适合VHDL的初学者使用.

说明：  matlab bpsk with rayleigh performance expirement

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.

EDA技术及其应用《序列信号发生器的设计》，包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)

基于alteraCPLD芯片的VHDL点阵滚动显示源代码-VHDL-based alteraCPLD chip dot matrix rolling display the source code

VHDL硬件描述语言与数字逻辑电路设计,学习VHDL的好资料-VHDL hardware description language and digital logic circuit design, VHDL learning good information

说明：  quartusII 9.1，位同步提取电路，可以实现位同步时钟提取，其中包括分频器，和由D触发器以及与门组成的鉴相器模块。(Quartus II 9.1, bit synchronous extraction circuit, can realize bit synchronous clock extraction, including frequency divider, phase discriminator module composed of D trigger and and gate.)

利用stm32F407实现的等精度测频，可以精确测量频率，误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)

An odd parity checker as an FSM using VHDL

8位深，9位宽FIFO VHDL源码设计，如需改进可在此基础上扩展-8 deep, 9-bit wide FIFO VHDL source design, for improving on this basis can be extended

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)