Memory Slave

异步的fifo,写时钟和读时钟相互独立，能够对数据进行缓存处理。希望对大家有用(Asynchronous fifo, write clock and the read clock independent of each other, capable of processing the data cache. I hope useful)

8051core-Verilog FPGA

vhdl code fpga for lcd 2*16

说明：  基于fpga的数字图像处理原理及应用源码(The principle and source code of digital image processing based on FPGA)

用verilog语言实现codic算法，按照原理敲出的代码，经仿真代码正确，效果理想

EDA技术及其应用《序列信号发生器的设计》，包括源文件。(EDA technology and its applications " sequence signal generator design, including source files.)

说明：  LVDS De-serialization

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

说明：  寄存器设计文件，寄存器输入输出以及读写控制，寄存器的配置(Register design and read-write control)

实现的电子钟，资料非常全面，是一次课程设计的大作业，完成的质量很高。(Achieve the electronic clock information is very comprehensive, curriculum design job, completed high quality.)