8051 核verilog源代码

基于FPGA的16*16点阵中文LED显示，另带有几个简单的中文汉字的点阵数据。(FPGA-based 16* 16 dot matrix Chinese LED display, and the other with a few simple lattice data Chinese characters.)

半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)

可以进行连续uart串口读写999次以上不出错，已经检测成功(It can read and write serial UArt more than 999 times without error. It has been detected successfully.)

韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验(Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and keystrokes 4 experimental statistics)

Verilog写的88E1111 GMII接口驱动代码,仿真通过，使用的是Xilinx的三态以太网IP核。

VHDL 语言实现 38译码器 文件中包括 程序 源代码 还有 testbench 测试程序(38 decoder VHDL language implementation, including program source code file, there are testbench test procedures)

说明：   基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)

quartus license dede(quartus 11.0 license)

利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)

Image Embedded VHDL Code by using watermarking technique