双向使用VHDL仿真环境转移登记环节

基于FPGA的17阶FIR滤波器VHDL代码及说明文档-fpga fir

DES加密算法的VHDL实现,采用流水线技术实现(The VHDL implement of DES encrypt algorithmic)

说明：  用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写(verilog ise divider)

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)

xilinx提供的频率发生器的VHDL源码，可以运行在spartan3的学习开发板上。-xilinx the frequency generator VHDL source code, spartan3 can run in the learning development board.

说明：  isa MEMORY PLAN eu biu asm

说明：  adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)

sdi音频嵌入及解嵌代码,代码使用Verilog HDL语言(SDI audio embedding and decoding code, the code using Verilog HDL language)

俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials