是vhdl语言，在fpga开发板上实现十进制技术（7段数码管显示），包括复位，清零，计数使能。...

电子时钟VHDL程序与仿真的vhdl源代码-Electronic clock and simulation of VHDL procedures vhdl source code

VHDL设计的功能齐全的交通灯程序，经过仿真一切功能符合要求。-VHDL

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

cyclone3_handbook-datasheet

说明：  qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

4weimimasuo 可运行 可仿真 -aetgdffh tghj tjfgj fdg vbn t

一种压缩感知信号恢复算法，针对贪婪迭代类算法中的正交匹配追踪（OMP)算法的改进。OMP在每次迭代过程中选择出的原子并不是最优的，无法使本轮迭代中残差的减少最大化。本例程实现了改进的最优OMP算法，即Optimised_OMP，保证每次迭代选出的原子与已选出的原子序列所构成的平面正交，因而可以使残差下降的更快，从而加速算法收敛。(A compressed sensing signal recovery algorithms track (OMP) algorithm and orthogonal matching algorithm greedy iterative class. The OMP selected atoms in each iteration of the process is not optimal, not be able to maximize the reduction of the residual in the current round of iteration. The routines to achieve the optimal OMP algorithm improvements that Optimised_OMP, to ensure that each iteration selected atoms with atomic sequence elected a plane orthogonal, and thus can make the residuals have declined even faster, thus speeding up the algorithm convergence.)

vhdl code for alu and detemines the basic components of alu unit in cpu system

cycloneIII_3c120_dev_power_demo atlera公司官方例程(cycloneIII_3c120_dev_power_demo atlera company official routines)