是vhdl语言，在fpga开发板上实现十进制技术（7段数码管显示），包括复位，清零，计数使能。...

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code

一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8

该程序实现的N位全减器，首先实现一位的减法器，之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.

Any change to the value of Mresults in immediate and phase-continuous changes in the output frequency

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

关于verilog的知识点和关键点的总结(Summary of knowledge points and key points of Verilog)

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)

A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition diagram, a state table and a schematic for your circuit. Design an alternate implementation using just three flip flops and draw a state transition diagram, state table and a schematic for your circuit. If your designs are extended to implement an n bit twisted ring counter, how many flip flops are required using each of the two approaches. In what situations would you prefer the first method? In what situations would you prefer the second?

等精度测频法，有需要的可以下载看看哟，word中包含的代码(Equal Precision Frequency Measurement Method)