vhdl code for alu and detemines the basic components of alu unit in cpu system

this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.

Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)

基于xilinx公司的SPARTAN6系列芯片的高速全双工串行收发器(high-speed transceiver based on spartan 6 of Xilinx PFGA)

verilog source code for SD card SLAVE DEVICE IP-Core

基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)

NIOS II IDE 编程， 定时器测试程序，仅供参考。-NIOS II IDE programming timer testing procedures, for information purposes only.

Brazo robotico proyecto para laboratorio

利用GPIO口模拟I2C通信，驱动富士通MB85RC系列铁电存储器 ** 支持的型号：MB85RC64/64V,MB85RC128/128V,不支持MB85RC16/16V(The master inputs the device address word (8 bits) following the start condition, and then the slave outputs)

用verilog语言编写的串口读写程序，波特率可调，亲测可用。(this is a program for UART by verilog, which is useful.)

An Alarm Project Writen in VHDL for FPGA Devices