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rectifier
三相PWM整流,实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ,can maintain the stable DC voltage)
- 2012-11-28 09:19:54下载
- 积分:1
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本例为电子琴VHDL程序原代码,电子琴,可实现基本功能
本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of
- 2022-03-23 15:59:38下载
- 积分:1
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led5604
5604FPGA驱动,能显示数字(5604里面为4个595)(5604 FPGA driver, able to display digital (5604 contains 4 595))
- 2020-06-19 18:00:01下载
- 积分:1
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脉动进位加法器
设计的结构是纹波进位加法器,但执行的操作是加法和减法,两种操作都是32位的,具体取决于控制信号。如果控制信号为“1”,则选择减法,然后选择“0”,然后选择加法
- 2022-02-02 17:58:16下载
- 积分:1
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Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.
周立功Verilog HDL黄金参考指南,学习VerriLog的东西。-Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.
- 2022-04-28 19:53:04下载
- 积分:1
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sd_models_verilog
测试过可用的SD仿真模型,VERILOG语言(SD card simulation modle, test OK)
- 2021-02-26 20:09:37下载
- 积分:1
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zuoye2
主要编写了一组二进制数据通过根升余弦滤波器后的波形,但并没有使用ISE内部的FIR滤波器内核,该程序相当于编写了一个根升余弦滤波器。(Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.)
- 2013-09-18 15:24:13下载
- 积分:1
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SystemC-UART
基于SystemC的Uart模型-----文档(SystemC the Uart model of----- document)
- 2013-01-24 16:41:35下载
- 积分:1
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FSM_Robustness_Testing
基于有限状态机的健壮性测试研究。
关键词:健壮性测试;增强有限状态机;全球平台;安全通道协议(The Research of Robustness Testing Based on FSM)
- 2012-09-06 14:08:56下载
- 积分:1
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ALTERA NIOS处理器,用VHDL在QUARTUS下编写,用NIOS SHELL调试通过,实验LCD液晶显示...
ALTERA NIOS处理器,用VHDL在QUARTUS下编写,用NIOS SHELL调试通过,实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
- 2022-03-20 10:53:06下载
- 积分:1