利用verilog语言设计实现8路FIR滤波

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

VHDL硬件描述语言与数字逻辑电路设计―― VHDL语言的基本知识和设计逻辑电路的基本方法及NAX的使用-VHDL hardware description language and digital logic circuit design

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

这是一个用结构化语言编写的25抽头LMS算法建模.VHDL加法器/减法器、乘法器、延迟元件的代码分别编写并用LMS代码实例化。

华莱士树乘法器，运用了华莱士树状结构和布斯算法，提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)

FPGA课件，个人感觉不错，希望对大家有帮助(FPGA software, personal feel good, I hope all of you help)

Verilog code of SPI configurator for DAC AD7394 and AD7395

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

EDA-Verilog 编码原则，初学者必看！-EDA-Verilog coding principles, beginners must-see!

fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)