NiosII_mycpu

如果需要用verilog设计一项比较简单的功能，那么这个浅显易懂的程序能让你很快明白点阵的设计方法，尤其是对那些初学者(If you need to use a relatively simple verilog design features, then this easy to understand design of the program allows you to quickly understand the lattice method, especially for those who are beginners)

说明：  基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。(The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations.)

Parallel to Serial converter Module

高精度直流信号源，DAC1220，20位分辨率，双极性输出(High-precision DC source, DAC1220,20 bit resolution, bipolar output)

这是波发生器的顶层。它直接实例化 I/O 垫和实现设计所需的所有子模块。

该资料基于FPGA实现USB2.0的高速传输，即CY7C68013A芯片的数据传输，包括FPGA与上位机之间数据的相互传输，CY7C68013A的传输速率最高可达480M/S。(The FPGA-based high-speed data transmission USB2.0, that CY7C68013A chip data transmission, including the mutual transmission of data between the FPGA and the host machine CY7C68013A transfer rate up to 480M/S.)

实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)

本代码主要完成了一个以FPGA为平台的模拟电梯控制器。该设计以Xinlinx 公司Spartan3E  250  板为平台，结合了LCD1602外设和rs232串口发送外设，成功的实现了对一个三层楼的电梯实时运行状态的模拟，1602实时显示电梯及门的状态，并通过串口将当前楼层发送给电脑。代码语言为Verilog HDL.本设计使用的算法思想有三：1、将多个输入信号合并为一个信号。2、Moore 状态机的使用3、电梯多个状态的处理以及处理原则 共同学习，共同进步。

黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)