可编程波发生器

Cordic 算法的设计处理实施 sin 和 cos 角度对于笛卡尔坐标。

listing program clock

从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)

该代码实现了FPGA对USB芯片68013的读写，语言是VERLOD，试验通过。(The code to achieve the FPGA read and write 68013 on the USB chip, the language is VERLOD, through the test. )

说明：  基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)

QPSK调制的载波频偏估计，是一个可以调用的函数。接收端进行了一系列的处理。经典的L&R法(QPSK-carrier frequence offset estimation_ L&R)

基于FPGA，利用VHDL语言对小车循迹进行设计。(Car tracking)

mike11河道断面处理软件，将断面格式写成11要求的格式(MIKE11 river section processing software, the section format 11 format )

图像去雾算法FPGA实现，使用xilinx Vivado开发环境(Image dehazing algorithm FPGA implementation using xilinx Vivado development environment)

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)