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BmpDecoder
适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
- 2011-02-11 16:43:45下载
- 积分:1
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edge_detect_p
用于检测信号上升沿,输出与时钟相关的正脉冲(Detect the rising edge of the signal)
- 2012-03-27 14:49:21下载
- 积分:1
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等精度测频率
说明: 利用stm32F407实现的等精度测频,可以精确测量频率,误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)
- 2020-06-19 13:00:02下载
- 积分:1
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Verilog 下 16位除法算法程序,高精度,固定17个时钟周期
Verilog 下 16位除法算法程序,高精度,固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
- 2022-01-27 13:18:06下载
- 积分:1
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Spartan6_GTP_PCIe_xfest_2009_v1_0
采用Xilinx公司的Spartan6 FPGA设计PCI Express的详细参考资料(Xilinx' s PCI Express, Spartan6 FPGA design, detailed reference information)
- 2012-08-30 10:01:33下载
- 积分:1
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PWM
说明: 脉冲宽度调制,VHDL代码编写,包括QUARTUSII和MODELSIM工程以及testbench(Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench)
- 2020-11-26 09:49:31下载
- 积分:1
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123.rar
請設計一個8位元移位暫存器,規格如下:
當控制線S1,S2輸入為00時,平行載入;
當控制線S1,S2輸入為01時,在一時脈內向右shift 1位元;
當控制線S1,S2輸入為10時,在一時脈內向右shift 2位元;
當控制線S1,S2輸入為11時,在一時脈內向右shift 3位元
(Serial Adder)
- 2009-12-08 00:02:56下载
- 积分:1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上用硬件描述语言实现一个ROM存储器。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 development board with hardware description language to achieve a ROM memory.
- 2022-08-23 17:16:15下载
- 积分:1
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Amp-diagrams_pack
Diagram and how-to-make instructions pack of 6 diferent Amplifiers
- 2010-10-24 18:40:43下载
- 积分:1
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用状态机对A/D转换器0809的采样控制电路的实现。工具:Quartus ii 6.0 语言:VHDL...
用状态机对A/D转换器0809的采样控制电路的实现。工具:Quartus ii 6.0 语言:VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL
- 2022-05-14 13:34:13下载
- 积分:1