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verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency

Program for Code Gerneration

spartan605评估板测试代码。xilinx官方资料(spartan605 uation board test code)

一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)

说明：  vhdl常见小实验代码，包括二进制比较器，4选1,8421十进制，8421转化成格雷码，8421余三码，分频器，数据码译码器，二进制减计数器，四位环形计数器等(VHDL common small experiment code)

hdlc协议的封装与解析，fsc校验，完整的例程代码(Decode and Encode an HDLC packet ，using FCS16 calculation)

这是一个瑞萨R78/G13的SPI演示程序，详细的放置了说明，很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)

说明：  基于IIC协议的EEPROM模型，可实现串行数据转并行数据，并行数据转串行数据，分为EEPROM模块，EEPROM_WR模块，signal模块，Top模块(The EEPROM model based on IIC protocol can convert serial data to parallel data and parallel data to serial data. It is divided into EEPROM module and EEPROM module_ WR module, signal module, top module)

（1）MTI （2）用FFT实现MTD （3）用FIR滤波器实现MTD ((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)

the 8 bit alu by verilog