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并串转换
利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。
- 2023-06-03 10:20:03下载
- 积分:1
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priorityencodtest
parity encoder test bench
- 2015-02-08 00:32:00下载
- 积分:1
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manchester_verilog
manchester_verilog源代码(manchester_verilog source code)
- 2008-07-11 08:50:53下载
- 积分:1
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FFTbased-on-FPGA
基于FPGA的快速傅里叶变换。使用ISE软件以及MATLAB验证。(FFT based on FPGA)
- 2014-09-25 12:51:52下载
- 积分:1
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verilog支持noise噪声的端口port
verilog支持noise噪声的端口port, 可以用于仿真运行.
评估噪声影响
Verilog port that supports noise and can be used for simulation run.
Evaluate noise effects
- 2022-07-25 10:35:21下载
- 积分:1
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quartus II中文用户教程(英文版的完全翻译)
说明: quartus II中文用户教程(英文版的完全翻译),和一切爱好可编程器件的同仁共勉之(Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi)
- 2020-12-21 14:19:08下载
- 积分:1
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cpu
说明: 一个简单的CPU设计,支持add,sub,mvi,mv四条指令,用Verilog语言编写,在Quratus II上编译通过,仿真正确。(A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.)
- 2011-04-09 12:22:09下载
- 积分:1
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UART串口传输的Verilog RTL
uart串口传输的verilog RTL级源码,已通过仿真验证。文件主要包含发送、接受位处理,发送、接受字节帧处理,对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps
- 2022-01-28 20:31:09下载
- 积分:1
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Core1553BRT_EBR_EV_20
actel公司用于1553总线的1553BRT-EBR核心代码 包括文档和代码非常有用(Actel company for the 1553 bus 1553BRT-EBR core code, including documentation and code is very useful)
- 2021-05-06 18:58:37下载
- 积分:1
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code
说明: 基于蜂鸟E203riscv系统的DMA外设代码(DMA code based on hbird_e203 system)
- 2021-04-14 13:38:55下载
- 积分:1