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table-for-sin-functionof-
DDS中的正余弦生成,初始相位相差90度,可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)
- 2013-12-17 22:09:56下载
- 积分:1
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VGAtuxiangxianshi
用FPGA实现 VGA显示的图像显示控制器设计
用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design
Using VHDL hardware implementation is colored stripes appear above the screen)
- 2014-05-19 14:07:57下载
- 积分:1
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decode
用Verilog实现汉明码编码,经测试可正确使用,代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)
- 2017-03-10 19:28:21下载
- 积分:1
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交通灯电路,南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭,数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。...
交通灯电路,南北方向和东西方向分别按绿灯、黄灯、左拐灯、黄灯、红灯的顺序两灭,数码管显示相应的灯亮的时间的倒计时。已通过编译和仿真。-Traffic light circuit, north-south direction and east-west direction respectively green, yellow light, left light, yellow light, red light destroy the order of two, a digital LED display lights the corresponding period of the countdown. Has passed the compilation and simulation.
- 2023-02-22 23:25:03下载
- 积分:1
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laplace
Laplace可以应用于图像的锐化,根据其原理,对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)
- 2020-07-15 18:28:50下载
- 积分:1
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Verilog教程-夏宇闻
verilog 教程 PPT版本 语法 结构 设计技巧等(Verilog tutorial PPT version)
- 2018-02-26 11:13:55下载
- 积分:1
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gamefive
高精度小数除法器设计与实现。
在FPGA开发板上实现小数除法器,输入输出信号N_in [15:0], D_in[15:0],N_in[15:0]小于D_in,即被除数小于除数,输出商Q_out[15:0]中Q[15]一定为0,Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)
- 2017-01-01 17:32:25下载
- 积分:1
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人脸识别(3D)
说明: 基于高清视频的3D人脸识别源代码,四万多行,经过FPGA实际验证,最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分:1
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vhdl,无进位同步计数器,完成6进制加,输出6进制序列数
vhdl,无进位同步计数器,完成6进制加,输出6进制序列数-vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences
- 2022-09-12 08:25:03下载
- 积分:1
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用VHDL硬件描述语言实现的对FPGA(Cyclone II)的配置的VHDL源代码。...
用VHDL硬件描述语言实现的对FPGA(Cyclone II)的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.
- 2022-07-11 15:27:50下载
- 积分:1