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src
说明: 实现UDP的网络传输,在PC建立UDP的服务器,向fpga的ip:192.168.0.25发送数据,实现回环通讯。(The network transmission of UDP is realized. UDP server is set up in PC, and the data is sent to IP: 192.168.0.25 of FPGA to realize loop communication.)
- 2020-09-05 20:39:29下载
- 积分:1
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VHDLman
VHDL book for reference
- 2010-01-18 17:40:26下载
- 积分:1
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usbhostslave
说明: USB主机和设备的verilog代码,实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)
- 2005-09-13 11:34:09下载
- 积分:1
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Риторика_Зачетная работа
说明: access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
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verilog hdl coding DDR sdram control for fpga
verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
- 2022-03-23 21:20:26下载
- 积分:1
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last
verilog,FPGA的TDC电路设计(verilog ,TDC base on FPGA)
- 2021-01-04 18:48:54下载
- 积分:1
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VGA显示接口的verilog控制程序。VGA显示驱动控制
VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动-VGA display interface Verilog control procedures. Control for VGA display driver
- 2022-04-10 10:17:35下载
- 积分:1
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AMBA APB桥VHDL
这是一个AMBA APB桥实现VHDL。这包括主人,奴隶和试验台试验桥。我已经测试功能。
- 2022-06-02 20:02:44下载
- 积分:1
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track_version2
说明: fpga实现相关滤波算法中的CSK算法,采用仿真的方式验证结果
fpga是xilinx
仿真工具是vivado2018.2
语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation
FPGA is Xilinx
The simulation tool is vivado 2018.2
Language is Verilog)
- 2021-04-29 16:08:42下载
- 积分:1
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fpga_coder_module
本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)
- 2021-04-21 01:58:50下载
- 积分:1