参数化 FFT

fpga paper function fff(fpga paper function)

4tap FIR filter in verilog code

AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)

用verilog语言编译的pci协议实现，而且有具体的电路图(Compiled with the verilog language pci protocol implementation, but also the specific circuit)

vhdl testbentch 编写模板。非常实用-vhdl testbentch prepared templates. Useful

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

xilinx 的8B10B编解码源码, 里面有仿真模型,用以测试验证(xilinx 8B10B encode/decode source)

fpga code for pong game

Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.

FPGA入门点亮一个LED灯，作为FPGA入门级程序(FPGA is)