一个在FPGA芯片上实现UART功能的vhdl源代码，提供了UART的集成

VHDL operators basics

IEEE Standard VHDL language

一款非常实用的8051IPcore,本人现在做soc的控制部分就是它。(A very useful 8051IPcore, I now control part of the soc is doing it.)

加法计数器的VHDL工程，程序，仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU

数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.

说明：  利用fpga实现gmsk的调制并仿真，全部代码(Fpga implements gmsk)

使用并行结构对32位数据进行前导零检测，使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)

fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)

用于检测信号上升沿，输出与时钟相关的正脉冲(Detect the rising edge of the signal)

蓝牙HCI―UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design