I2C interface standard modeling source

FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器(The VERILOG code FIFO write comprehensive Verilog FIFO memory)

最大最小值寻找程序，可以实现自动查找最大值与最小值(min_max_finder)

OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders

四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model

实现verilog读写txt文件，从sut.txt从读取数据，进行操作后，写入out.txt(Realize verilog read and write txt file)

上传的是基于Xilinx的新出的开发板Zedboard的一个简单的知道文档，希望对有关同学有所帮助。(Uploaded a simple know the document based on Xilinx' s new development board Zedboard the hope that some of the students to help.)

基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)

ALTERA on chip fifo. this document is from altera. good resouce

verilog ADPLL file with testbench

gps C/A码生成 生成gps32颗卫星伪码，方便，经过测试(gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested)