this document is in two MAXplusII environment through the development and operat...

Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现(Ethernet 10GE MAC)

这篇文章主要是概要的阐述了如何使用-quartusⅡ+Modelsim+synplify pro，来设计FPGA系统。-This is a summary of the main article on how to use the-quartus Ⅱ+ Modelsim+ synplify pro, to design FPGA systems.

波形产生器：用VHDL编写的波形产生器程序-Waveform Generator: Using VHDL prepared waveform generator procedure

说明：  nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)

该代码为VHDL语言描述的AD579 SPI通讯程序，包括一些代码注解。(Thisis a SPI communication promgram of AD5791 designed with VHDL which compared with some discreption.)

通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

千兆以太网设计，包括组包解包，可以实现大数据传输功能。(Unpack the gigabit Ethernet is designed, including group package, can realize large data transfer function.)

自己完成的项目，成功用vhdl语言实现数字跑表，可存储。

D-flip flop vhdl implement code

用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.