this document is in two MAXplusII environment through the development and operat...

中值滤波实现。选择在Vivado软件上采用Verilog语言来编写中值滤波算法，搭建出完整的数据处理系统架构，通过仿真和验证来判断数据的处理效果，并在实际的设计过程中根据出现的问题提出解决方案。(Median filter implementation. The author chose Verilog language to write the median filter algorithm in Vivado software, built a complete data processing system architecture, judged the data processing effect through simulation and verification, and proposed a solution according to the problems in the actual design process.)

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分，顺序语句的执行方式十分类似于普通软件语言的程序执行方式，都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)

DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

Cadence_manual_1.2.pdf