this document is in two MAXplusII environment through the development and operat...

使用VHDL在CPLD上设计UART的一个项目-VHDL design UART

基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)

UART自适应波特率发生器，其中是以文档的形式来介绍怎样实现UART波特率发生器的实现(Adaptive UART baud rate generator, which is in the form of a document to describe how to achieve the realization of UART baud rate generator)

GPIO LED 测试工具源代码，可以用来检测开发的主板GPIO LED设备是否工作正常(GPIO LED test tool source code, can be used to detect the development of motherboard GPIO LED device is working properly)

Farrow 滤波器设计经典文章，作者是：FM.Gardner，farrow滤波器设计的始祖，经典值得推荐！（两篇文章）(Farrow filter design classic article, the author is: FM.Gardner, farrow filter design ancestor, classic worth recommending! (Two articles))

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER

该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行(This file is booth multiplier verilog code, after the final simulation, can be directly run)

验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)

设计一个可容纳四组参赛的数字式抢答器，每组设一个按钮供抢答使用。抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用；设置一个主持人“复位”按钮，主持人复位后，开始抢答，第一答对一次加1分，答错一次减1分

DDS的VHDL程序，相当好，值得下载，共享才是王道(DDS, VHDL program is quite good, worth downloading, sharing is king)