cadence verilog lanaguage and simulation course

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

usb控制器，有VHDL实现的，还有C++的源码，可以编译-usb controller, there is the realization of VHDL, as well as C++ source code can be compiled

内容1：哈尔滨工程大学信息与通信工程学院的课件-适合初学VHDL语言的人。内容2：VHDL语言详解的讲义。-1: Harbin Engineering University College of Information and Communication Engineering of software- suitable for novice VHDL language. Content 2: VHDL language of the notes explain.

我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。(The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.)

资源描述利用VHDL语言编写的浮点乘法器，可自定义浮点数位数，即乘数的参数化。具体为二进制有符号的浮点乘法器，二进制补码进行浮点运算。浮点数的表示是仿照IEEE格式，设置成自定义形式。

基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)

FPGA实现的LCD接口，VHDL编程,FPGA芯片为ALtera公司的EP2c35-FPGA realization of the LCD interface, VHDL programming, FPGA chips for Altera

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)