cadence verilog lanaguage and simulation course

看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来-saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks

说明：  这个事VHDL基础知识，内面主要内容是编码器的插V过程，值得下载学习！(it is really useful for those who never touch it!)

说明：  offset_cancellation code for matlab to hdl

用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)

16 bit switch input view in hexa format on 7seg display

说明：  利用verilog写的PWM 程序，来实现产生呼吸灯的效果。(Using xerilog to generate breathing lamp)

程序主要用硬件描述语言（VHDL）实现： 单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems

清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大！！(Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !)

This rar files contains the presentation about FPGA and CPLD .

Multiplexer styles in VHDL