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control_s
数控机床 多轴插补原理积分算法,实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
- 2021-05-07 09:58:36下载
- 积分:1
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HUAWEI_FPGA
华为内部资料,华为FPGA全套资料,包括华为的专利设计(Internal information Huawei Huawei FPGA complete information, including Huawei' s patented design)
- 2020-12-21 18:19:08下载
- 积分:1
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sd_ctrl
利用verilog实现对SD卡的控制,可以实现对SD卡的读写。(Verilog SD)
- 2020-12-27 21:49:03下载
- 积分:1
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3g-sdi
3g-sdi驱动器,用于全高清视频FPGA解决方案(3g-sdi driver)
- 2013-08-06 21:59:37下载
- 积分:1
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Xilinx
说明: 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。
LDPC,
CPRI,
Turbo,
Polar,
JESD204B/C
HDMI1.4/2.0,
MIPI CSI-2,
MIPI DSI
AXI CAN
AXI USB2.0
SD Card Host
Reed-Solomon Decoder/Encoder
10G Enthernet MAC
25G Enthernet MAC
40G Enthernet MAC
50G Enthernet MAC
100G Enthernet MAC
RS Encoder/Decoder
Display Port/ DP
Video Test Pattern Generator
RapidIO
tri mode ethernet mac(LDPC,
CPRI,
Turbo,
Polar,
JESD204B/C
HDMI1.4/2.0,
MIPI CSI-2,
MIPI DSI
AXI CAN
AXI USB2.0
SD Card Host
Reed-Solomon Decoder/Encoder
10G Enthernet MAC
25G Enthernet MAC
40G Enthernet MAC
50G Enthernet MAC
100G Enthernet MAC
RS Encoder/Decoder
Display Port/ DP
Video Test Pattern Generator
RapidIO
tri mode ethernet mac)
- 2020-03-11 15:40:45下载
- 积分:1
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Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。...
Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis
- 2022-03-21 18:04:20下载
- 积分:1
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turbo[1].tar
turbo码的verilog程序,有意者请下载。(turbo code verilog procedures Interested parties please download.)
- 2021-01-14 17:58:46下载
- 积分:1
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transmittermegafunction
lvds transmitter megafunction (lvds transmitter megafunction)
- 2008-03-09 19:40:03下载
- 积分:1
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AES 128 Crypto Core
Mini AES
Advanced Encryption Standard (AES) implementation with small area/resources utilization.
Features
- Encryption and Decryption unit in single core.
- 2023-01-28 07:05:04下载
- 积分:1
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在QuartusII运用AHDL语言,首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位;再设计状态机用来检测串行数据流中的序列。...
在QuartusII运用AHDL语言,首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位;再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变PN码结构可以作为通用数列检测器-QuartusII use in AHDL language, the first PN generator designed to generate a data stream 11 throughout the cycle has an effective data = 2047 re-designing the state machine used to detect the serial data stream in sequence. The use of two counters were counting on the PN code, as well as counting the number of sequences occur. Changes in the structure of PN code series can be used as general-purpose detector
- 2023-03-11 09:20:03下载
- 积分:1