该源码为VHDL语言编写的分频器，在W

FPGA based design and Implementation of Advanced Encryption Standard

单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)

FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures

file_read vhdl code provide by my teacher for reading file into FSM-file_read vhdl code

基于FPGA的RS编码器设计，verilog hdl语言。(RS encoder FPGA-based design, verilog hdl language.)

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

说明：  一个完整的雷达系统仿真MATLAB程序，非常具有参考价值(A complete radar system simulation MATLAB programs have great reference value)

ModelSim的使用如何操作和使用以及安装如何安装

使用verilog写的频率计，可切换档位(Frequency counter using verilog write switch stalls)

说明：  用VERILOG编写的一个可以实现VGA显示的程序.....(Prepared using a VERILOG VGA display program can .....)