使用 nios 和 verilog hdl tcp/ip 通信通过使用来创建 DM9000A，它可以起到 5 Mb/s

VHDL Bible. It is a must read for any front end vlsi designer.

LDPC encoder and decoder, very simple

decoder 2-4 digital core

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

verilog实现mp3解码程序，包括testbench(mp3 decoder verilog implementation procedures, including the testbench)

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

FPGA 12864显示程序 VHDL程序！！(FPGA 12864 show program )