使用 nios 和 verilog hdl tcp/ip 通信通过使用来创建 DM9000A，它可以起到 5 Mb/s

本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。 (In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)

控制电话信令 完成忙碌 等待 回铃音振铃等(Signaling complete control over telephone ring so busy waiting ringback tone)

Quartus? II 相关的语言 详细介绍了VHDL verilog软件开发过程(Quartus ? II related language detailed introduces the verilog VHDL software development process )

说明：  本文档对LTE进行了详细的介绍，是一本LTE入门的好书(This document is a detailed introduction to LTE, is a good book to get started with LTE)

说明：  ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

A programming language that can decode alpha numeric

说明：  led blinking program.................

2ask调制与解调的源代码，经过测试可用(2ask modulation and demodulation source code is available, tested)

NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助(NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful)

说明：  combinatorial modules