标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合...

block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)

I2C verilog 源代码 非常好的代码，大家可以-I2C verilog source code for a very good code, we can

vhdl实现的鼠标协议，代码可读性高，适合作为参考案例。-VHDL realize mouse agreement, the code readable, suitable as a reference case.

产生svpwm波形，可以参考下载,以便学习交流(gennerate SVPWM wave)

本实验主要是在FPGA上实现FIR数字滤波器的功能，不仅有工程文件，还具有论文资料。(This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information.)

des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language

Control Unit VHDL code. Xilinx Spartan 3E board

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga