here is realized simple FIFO stack in vhdl. very simple example, but very help...

完整版的乘法器.相信对初学者有不小的提高-The full version of the multiplier. I believe there is not a small improvement for beginners

图书馆IEEE；

串口模块程序，可以实现串行发送和接收功能，比特率可以不断调整，数据的长度是可以改变的-Serial port module program, you can achieve the serial send and receive functions, and bit rate can be continuously adjusted, the data length can be changed

VHDL_COUNTING 与 4 使脉冲和使用 3 按钮了，下来，停止 （Mạch đếm với 4 xung ENA sử dụng 3 nút nhấn lên，xuống và dừng lại）

PLL 锁相环verilog程序 可以直接使用(The PLL can be used directly good use)

to learn bout development of vhdl code

xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)

用IF语句实现秒表功能的代码，显示范围在000至99.9.(Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.)

一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter

四位十进制频率计的顶层控制模块，用于生成测频需要的复位及控制信号-four decimal frequency of top-level control modules, used to generate the required frequency measurement and control signals reset