here is realized simple FIFO stack in vhdl. very simple example, but very help...

迫零-串行干扰删除检测的程序，包括16QAM和QPSK(Zero forcing- Interference Cancellation detection procedures, including 16QAM and QPSK)

FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)

1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)

Priority encoder in VHDL.

Use full for knowing board details while making projects on FPGA and matlab simulations

VHDL2verilog的程序，相信对大家很有帮助-VHDL2verilog procedures, I believe very helpful to everyone

本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book

VGA controller : Genarate a VGA signal from your inout information as color info of each pixel

it s vhdl program for decoder