DUC数字上变频设计

verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)

mipi转LVDS接口， verilog代码，在lattice 芯片上使用，已验证(MIPI to LVDS interface)

片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

linux cmd line download script

采用verilog实现的有限域GF(28)弱对偶基乘法器，本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ，多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7}，弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)

uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

VGA显示原理与VGA时序实现论文,详细介绍了VGA的原理 (Principle and VGA VGA display timing to achieve paper, detailing the principles VGA)

说明：  uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)