FPGA简:讲述了FPGA的基本概念、结构、发展

用于实现两个数相加的vhdl代码，在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler

SED1330/1335/1336/E1330液晶显示控制器及51汇编源程序.液晶显示程序,显示图形及汉字.-SED1330/1335/1336/E1330 LCD controller and the source of 51 Series procedures. LCD procedures, and show pictures of Chinese characters.

基于FPGA的RS编码器设计，verilog hdl语言。(RS encoder FPGA-based design, verilog hdl language.)

DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

用状态机对A/D转换器0809的采样控制电路的实现。工具：Quartus ii 6.0 语言：VHDL-State machine used for A/D converter sampling control circuit 0809 is achieved. Tools: Quartus ii 6.0 Language: VHDL

VHDL book for reference

verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

自编的64B/66B编码程序，下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)

非常好的verilog书 国际牛人写的 适合各个阶段学习的人(Very good Verilog books were written in the international cattle suitable for the various stages of learning)