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实验课的作业,包括半加器、全加器、加/减法器,使用逻辑图和VHDl描述,包括分析和报告。...
实验课的作业,包括半加器、全加器、加/减法器,使用逻辑图和VHDl描述,包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
- 2022-12-20 07:25:03下载
- 积分:1
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CH2CH1VHDL 数字电路参考书所有程序3
CH2CH1VHDL 数字电路参考书所有程序3-CH2CH1VHDL digital circuit reference all three procedures
- 2022-05-29 17:53:40下载
- 积分:1
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可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。
可在FPGA上运行的8051 IP core,是学习FPGA及SPOC的好资料。-FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.
- 2022-03-26 18:10:19下载
- 积分:1
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PS2_kebord_controller
PS2键盘控制器的VHDL源码,用FPGA直接读取键盘的输入并显示。(PS2 keyboard controller VHDL source code, with a direct FPGA to read keyboard input and displayed.)
- 2010-10-15 18:13:27下载
- 积分:1
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ldpc_decoder_802_3an_latest.tar
LDPC encoder and decoder, very simple
- 2015-03-10 05:35:38下载
- 积分:1
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用verilog实现FSK调制,称为IP核来实现模块…
用Verilog实现FSK调制,调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
- 2022-03-15 17:40:05下载
- 积分:1
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vhdl应用汇编所写的关于电梯的详细程序
vhdl应用汇编所写的关于电梯的详细程序-Applications written in VHDL compilation of detailed procedures on the elevator
- 2022-03-18 06:59:58下载
- 积分:1
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VGA
VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)
- 2017-12-07 20:55:10下载
- 积分:1
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maichongceliang
对于已获得的脉冲包络采样序列,需测量的脉冲特征参数主要有:脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中,脉冲波形的形状是各种各样的,但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等,脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
- 2009-07-08 14:32:08下载
- 积分:1
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我是VHDL的初学者,这是我自己编译的简单的几个VHDL码,功能有3...
我是VHDL的初学者,这是我自己编译的简单的几个VHDL码,功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。
希望能和其他初学者一起讨论学习,并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
- 2022-05-14 07:13:44下载
- 积分:1