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multifre
说明: 资料的内容是实现旋转机械同步整周期采样的数据采集系统相关文献资料,包括鉴相信号如何倍频,机械振动信号相位如何检测等的实现方法。(Information content is for rotating mechanical synchronization synchronous sampling data acquisition system-related documents, including the Kam-believe number to harmonic mechanical vibration signal phase to detection of realization.)
- 2010-04-26 15:56:20下载
- 积分:1
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fft
FPGA实现FFT算法的源代码及工程文件,此工程为ISE工程项目。有详细的说明,可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)
- 2013-10-12 17:21:32下载
- 积分:1
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Norflash
用verilog hdl写的Norflash控制器,可实现单字节读写,扇区擦除。(Norflash controller edit by Verilog hdl,it can read or write by Byte,or erase the sector.)
- 2021-03-29 16:29:11下载
- 积分:1
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AES_128
AES 128 bit with various device interface on FPGA
- 2021-03-09 17:59:27下载
- 积分:1
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apb timer
说明: 是基于apb总线下的timer外设的rtl代码,主要包括apb_timer的master逻辑verilog,以及相应的开发文档,包括寄存器的描述,功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
- 2019-01-25 16:54:02下载
- 积分:1
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fifo
一个FIFO产生程序,主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)
- 2011-08-28 10:39:31下载
- 积分:1
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multi8x8
节约资源型 8位*8位 运算VHDL代码,采用串行运算,8 个时钟周期完成一次运算。QUARTUS下已验证(resource conservation-8* 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test)
- 2006-12-07 13:22:48下载
- 积分:1
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vivado2017+下的HDMI环路视频代码(AX7103)
在黑金AX7103板子上(A7)实现的demo工程中,存在一些bug。给与修正
- 2022-05-12 17:34:33下载
- 积分:1
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BCH3
BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)
- 2021-01-26 11:58:36下载
- 积分:1
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1 bit full adder
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:40:20 01/09/2019
// Design Name:
// Module Name: fulladder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fulladder(
input a, b, cin,
output s, cout
);
assign s=a^b^cin;
assign cout= a&b| b&cin | cin&a;
endmodule
- 2022-02-12 01:48:54下载
- 积分:1