基于优先级的调度

VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)

对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)

设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述，给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)

说明：  8051单片机mcu的ip核，文件语言为verlilog，内容包含alu/指令解码/ram控制/寄存器结构等(The IP core of 8051 MCU, the file language is Verilog, the content includes Alu / instruction decoding / ram control / register structure, etc)

xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)

交通灯的控制，分主干道和从路交通灯，主路优先，正常情况下，绿灯60s，红灯30S，黄灯5S(Traffic light control)

用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)

出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)

说明：  简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)

采用verilog语言基于查找表描述8b10b编码源代码(Using Verilog language to describe 8B10B encoding source code based on look-up table)