fpga通过usb 向电脑发送计数器的数据

实现与电脑端串行数据发送与接收，波特率为9600(Realize serial data sending and receiving with the computer terminal)

emif接口转axi接口，在多个项目中使用，功能完善(EMIF interface to Axi interface, used in many projects, perfect function)

synopse sv培训lab，是学习systemverilog非常好的资料，放心下载。(synopsis sv training lab)

说明：  FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)

用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

3 到 8 解码器使用 case 函数 玩得愉快

说明：  经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)

Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.