中山大学计组实验--单周期CPU设计

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

说明：  学习VHDL可以用得上，有很多实例，可以对照着自己写一些东西(VHDL can be useful to learn, there are many examples, can be done to write something)

1.設計一計數器，計算輸入信號（pulse）的高準位有多少個時脈週期，並將計數結果輸出至（cnt_value）。2.使用hw1_tb.v當Top level Testbench 。3.注意cnt_value只能在每次輸入信號（pulse）負緣後變化一次。 

说明：  SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

说明：  实现主干道交通灯显示，以状态机程序实现，并用数码管进行红绿灯倒计时的显示，内置计数模块，交通灯控制模块，数码管显示模块，并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)

说明：  高速流水的SDRAM控制器，最高速度可达速度在200M左右(high speed SDRAM controller)

自动售货机，根据所要的东西，自动收费，并进行找零(Vending machine, according to what you want to automatically charge and conduct Keep the change)

AD4003的Verilog程序，验证有用(Verilog code for AD4003)

16输入校验节点更新单元，实现分离、分类、比较，最终输出与端口对应的最小值(即除去自身以外的最小值)。内附仿真结果图，供大家理解。

使用一个寄存器型参数来实现16位数据传完成后寄存器地址加1