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cnt6
verilog实现的“六进制约翰逊计数器”。(verilog implementation of the " six hexadecimal Johnson counters." )
- 2009-09-18 19:11:18下载
- 积分:1
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huffman
huffman transform in vhdl language
- 2013-08-26 13:17:15下载
- 积分:1
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RS(204-188)decoder_verilog
采用verilog实现的有限域GF(28)弱对偶基乘法器,本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ,多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7},弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)
- 2016-06-12 16:31:51下载
- 积分:1
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altera实现的UDP协议(Verilog实现)
Verilog实现的udp协议,比网络上的资源更加丰富,想要了解altera tse相关源码,就大胆下载吧,给你想要的一切。
- 2022-04-27 08:25:46下载
- 积分:1
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emifa_ram
FPGA与DSP的EMIF通信,EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)
- 2020-12-01 15:49:26下载
- 积分:1
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ht66f0185-1
小家电常用芯片HT66F0185的UART 使用例子,已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)
- 2020-10-09 16:27:34下载
- 积分:1
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stm32adc12路采集DMA
adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)
- 2020-06-19 06:20:01下载
- 积分:1
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Micron_SDRAM_DDR2Simulation_model_Verilog
DDR2 SDRAM仿真模型,适合于ModelSim下工作,请先阅读readme(DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.)
- 2020-10-29 17:49:57下载
- 积分:1
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FPGA I2C IP
应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the
implementation of custom I2C slave devices. The core provides a means to read and write
up to 256 8-byte registers. These registers can be connected to the users custom logic,
thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used
to set the register address pointer, and write the register data. I2C reads are used to read
the register data. Successive data reads or writes result in data being read or written from
incremental register addresses. There is no limit on how much data can be read or written
in a single access, but the internal register address pointer will wrap round to 0 once it
reaches 255. Note that the address pointer is not initialized at reset, and the address
pointer must
- 2022-05-22 00:28:39下载
- 积分:1
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快速FFT的Verilog实现
快速傅里叶变换的模块,测试平台,verilog语言
- 2022-03-23 13:12:13下载
- 积分:1