各种加法器的 vhdl 代码

SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。(SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.)

一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加(A 32-bit floating-point adder can be both within the IEEE 754 format to add value)

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

cordic算法，实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)

FPGA实现BPSK调制，带Modelsim仿真，实际系统测试通过，载波信号，调制波信号频率可调(FPGA implementation BPSK modulation with Modelsim simulation, the actual system test, the carrier signal, modulated wave signal frequency adjustable)

利用VHDL实现CPLD（EMP240T100C5）的PWM输出-Using VHDL realize CPLD (EMP240T100C5) of the PWM output

verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦(verilog things properly used it, it is an essential learners verilog things oh)

说明：  使用ISE软件实现OFDM通信系统的框架搭建，完成上板前的仿真工作(Realization of OFDM communication system with ISE software)

c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去-51 Singlechip c language keyboard scanning procedures for transplantation to other hardware up

万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!