VHDL参考程序，他们的初学者参考使用

verilog HDL 4×4矩阵键盘驱动程序包括硬件电路图-verilog

QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)

串口控制器，基于vivado软件下开发，包含代码及管脚分配文件(Serial port controller)

硬件设计VHDL学习100例(站长推荐)-VHDL hardware design study of 100 cases (chief recommended)

FFT处理器设计及其应用研究，适合做fpga信号处理的技术人员参考-FFT processor design and applied research, suitable for signal processing fpga technology reference

使用430的四系点亮流水灯，内置有时钟函数，函数简单，值得一看(The four lines using 430 lit water lights, built-in clock function, the function is simple, eye-catcher)

产生svpwm波形，可以参考下载,以便学习交流(gennerate SVPWM wave)

数字钟，数字电子技术课程设计常用内容，基于basys3平台(Digital clock, digital electronic technology curriculum design commonly used, based on the basys3 platform)

利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module