VHDL参考程序，他们的初学者参考使用

这是一个nios工程，控制TFT液晶屏的程序。FPGA平台用Verilog HDL语言编写的，MCU软核程序有C语言编写。通过这一个完成的工程，你就会明白SOPC的一些实现方法。(This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization. )

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging

说明：  fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)

我自己当初用来求解arctan 暂时没有搞成ip形式 搞好了还要传git 这个代码还没有搞好，因为急需要下载东西 如果感兴趣可以联系我 邮件(this is a not full wrappered code very crude use chebyshev to caculate arctan function i m urgent to download a model from pudn so i do this.)

出租车记价器，使用vhdl语言编写的源码及其仿真。-Taxi price of devices in mind, use the source code written in vhdl and simulation.

北航夏宇闻的Verilog的PPT讲稿，挺经典的，适合初学者学习(Northern Xia Yu Wen' s Verilog the PPT script, very classic, suitable for beginners to learn)

应用背景Booth乘法器实现快速乘法algorithm.mainly用于通信和DSP组成的3块摊位重新编码，华勒斯树和超前进位addder关键技术超大规模集成电路设计，通信和DSP的应用，芯片设计，VHDL，Verilog程序，加法器和乘法器

vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.