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rs485_uart
说明: fpga的RS485代码,非常容易,适合学习(the code of rs485 in fpga, very easy,suitable for learning)
- 2019-07-11 14:24:54下载
- 积分:1
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VHDL语言写的频率计的程序,内带完整的技术报告
VHDL语言写的频率计的程序,内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report
- 2022-02-20 00:46:02下载
- 积分:1
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xapp1161
多相滤波系统的设计与实现,有MATLAB仿真程序,有sysgen的系统仿真,还有VHDL代码,其中还有FIR的系数参数等等(Polyphase filter system, the design and implementation includes a MATLAB simulation program, sysgen system simulation, and VHDL code, including FIR coefficient parameters, and so on
)
- 2021-02-15 17:29:47下载
- 积分:1
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tdm_latest[1]
TDM,就是时分复用。本程序完成4通道,没通道最多32路64K信号的交换,就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)
- 2010-07-07 15:28:06下载
- 积分:1
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VHDL描述的自定义交织器
交织器主要是对输入数据按照一定的规则打乱以便减少数据中过长的连0或者连1的出现。交织矩阵为行列矩阵,msgin为输入比特,msgout为交织输出比特,row和rol为交织器的行和列,可以通过改变col改变交织深度。先把输入的比特流数据改变为一个矩阵,再按照一定的方式输出为比特流数据
- 2022-03-15 22:36:53下载
- 积分:1
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wp_max_flash
FPGA中FLASH配置控制源码,VHDL和Verilog(FPGA source code in the FLASH configuration control, VHDL and Verilog)
- 2007-12-11 15:57:15下载
- 积分:1
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2004 SNUG of systemverilog
2004 SNUG of systemverilog
- 2022-09-09 13:40:02下载
- 积分:1
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canbus verilog实现,原代码文件
canbus verilog实现,原代码文件-canbus verilog implementation, the original source document
- 2022-06-15 18:20:23下载
- 积分:1
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Sys-gen
System Generator
- 2020-10-25 16:40:00下载
- 积分:1
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degilent atlys board ucf
;
- 2022-04-10 00:32:44下载
- 积分:1