Temperature measurement Using LabVIEW FPGA, Spartan3E, PMODTMP

乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

Xilinx FPGA using leftover multipliers and block RAM

vhdl,序列信号检测模块，此模块检测1110010，可改为任意序列，输出电位为1为检测出，否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0

imp book for cmos technology

altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

DES加密算法的VHDL实现,采用流水线技术实现(The VHDL implement of DES encrypt algorithmic)

黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)