登录
首页 » VHDL » 用FPGA实现IIC通讯的主控端,最简化的代码,占用最小FPGA资源

用FPGA实现IIC通讯的主控端,最简化的代码,占用最小FPGA资源

于 2022-07-10 发布 文件大小:218.79 kB
0 141
下载积分: 2 下载次数: 1

代码说明:

用FPGA实现IIC通讯的主控端,最简化的代码,占用最小FPGA资源-Use FPGA to come ture the main control of the iic comunication, the most simple code and using the least FPGA resource

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 《阿东+手把手教你学FPGA》完美公开版
    一本很好的教程,适合初学者,里面有详细的教程,很值得一看!!(A good tutorial, suitable for beginners, there are detailed tutorials, it is worth a visit!!)
    2018-06-20 19:41:52下载
    积分:1
  • RS232 data transmitter, suitable for beginners VHDL reference
    RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
    2022-03-15 09:13:00下载
    积分:1
  • 硬件设计vhdl_cpu1,1。您可以复制和分发该副本…
    硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.
    2022-02-06 23:06:37下载
    积分:1
  • Verilog languages with four arithmetic logic unit ALU, functional reference to 7...
    用verilog语言编写的4位算术逻辑单元ALU,功能参考74181,包含.v文件以及测试用.vwf文件-Verilog languages with four arithmetic logic unit ALU, functional reference to 74,181, including. V documents and testing. Vwf document
    2023-07-06 11:15:03下载
    积分:1
  • data_swith
    verilog 代码实现串并转换,有延迟(Verilog code and string conversion, delay)
    2011-07-31 23:58:17下载
    积分:1
  • Timing_Closure
    详细讲解时序约束培训教材,有利于更好对时序约束的理解(Timing constraints elaborate training materials, facilitate better understanding of the timing constraints)
    2010-08-12 20:02:33下载
    积分:1
  • GPU_LDPC+硕士毕设论文详解
    QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)
    2021-05-14 19:30:07下载
    积分:1
  • 两个加法器和乘法器与并行处理的使用…
    利用两个加法器和两个乘法器一起并行处理来实现
    2022-05-28 05:02:29下载
    积分:1
  • SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。 ODD_110BREG是一个3位的备...
    SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。 ODD_110BREG是一个3位的备份寄存器,寄存器中存放的是奇数帧的同步头,也就是110。 EVEN_9BHREG是一个8位的备份寄存器,寄存器中存放的是偶数帧的同步头,也就是10011011。这两个寄存器的初始值在系统一开始就打入。 -SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
    2022-05-15 03:11:22下载
    积分:1
  • TCM_Modulation
    TCM编码的调制端,采用8PSK,2/3码率的卷积码的matlab程序(TCM coded modulation client, using 8PSK, 2/3 code rate of convolutional codes of matlab program)
    2021-04-20 00:08:51下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载