用FPGA实现IIC通讯的主控端，最简化的代码，占用最小FPGA资源

Verilog经典教程，非常好的资料！值得一看！(Classic Verilog tutorials, very good information! Worth a visit!)

基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)

控制器灯具有线和无线控制器采用STC11F02做的(Controller for lamp wired and wireless controller using STC11F02 to do)

说明：  可以实现2PSK的信号调制，已经过Modelsim波形仿真(It can realize 2PSK signal modulation and has been simulated by Modelsim waveform.)

8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for

利用Quartus 综合简单的计时器功能，欢迎大家下载、参考。谢谢大家的支持！

说明：  bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)

VGA图象显示控制器设计,实现在VGA显示器上显示图象.-VGA image display controller designed to achieve the VGA display shows images.

writing testbench in system verilog

定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)