VHDL tutorial for beginning learner

曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0，低→ 高的跳变表示为1。每个码元中间都要发生跳变，接收端可将此变化提取出来作为同步信号，使接收端的时钟与发送设备的时钟保持一致-Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock

测试人体视觉的反应时间，可以作为vhdl编程的练习之用，也可以更进一步的开发成为具有商业价值的产品，这里面只是能够实现测试人体视觉反应时间的基本功能的程序-Test of human visual reaction time, can be used as VHDL programming exercises used can also be further developed into products with commercial value, there is only able to realize the human visual reaction time test the basic functions of the procedures

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

工作机制如下： 1、 系统上电,配置信息由片外加载到片上配置存储器中; 2、 执行某算法前，将此算法所有的配置包写入到配置包存储器中（配置包存储器包含在配置解析单元中）; 3、 配置解析单元解析配置索引,从配置存储器中选择相应的配置对可重构阵列及功能模块进行配置； 4、 阵列从外部中读取数据进行计算，计算结果写出到密文寄存器中； 5、 可重构阵列与功能模块计算的中间结果数据只与通用寄存器堆进行交互； 6、 阵列计算的中间结果通过通用寄存器堆缓存；

说明：  基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)

说明：  自己写的DES的verilog实现。输入输出实现了并转串。(DES algorithm implemented in verilog.)

跑马灯led_horse vhdl cpldfpga-led_horse vhdl cpldfpga

说明：  使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)

FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)

一个双向总线的vhdl实现-a two-way bus VHDL achieve