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DE2_115_Synthesizer
FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
- 2013-08-20 19:48:32下载
- 积分:1
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关于格 CPLD ufm 演示
ufm 演示关于格 CPLD,使用这个项目,可以使用关于格 CPLD 国米闪光
- 2022-02-21 06:54:53下载
- 积分:1
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pipelined_fft_256
说明: 256 点fft的verilog source codec以及testbench(256 point fft, with verilog source codec and testbench)
- 2019-11-02 14:16:07下载
- 积分:1
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A4_Uart_Top
串口! 这是一个使用的通信程序 , 非常好用。(serial port Serial port! This is a communication program used, very useful.)
- 2020-06-17 14:00:01下载
- 积分:1
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sim_uart
uart 收发器 verilog 代码,实现自收发功能
sys clk = 25m, baud 9600 停止位1, 无校验位;
代码实现了串口自收发功能,及把从 PC 收到的内容都发送会 PC, 其他波特率,自行修改代码即可,在 alter 的FPGA 上调试通过;
(verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
- 2010-10-10 21:49:46下载
- 积分:1
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AD转换
FPGA为altera的EP4CE10F17C8,AD芯片为TLC519,验证成功,可以进行小电压数模转换
- 2022-07-27 18:29:40下载
- 积分:1
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pl_read_write_ps_ddr
说明: PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重,常常需要将 PL 端的大量数据实时送到 PS 端处理,或者将 PS 端处理结果实时送到 PL 端处理,但是各种协议非常麻烦,灵活性也比较差,直接通过 AXI 总线来读写 PS 端 ddr 的数据,这里面涉及到 AXI4 协议,vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分:1
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modelsim输出文件代码演示 verilog
资源描述
modelsim输出文件代码演示 verilog 内含头文件和testbench.Verilog HDL是一种硬件描述语言(HDL:Hardware Description Language),以文本形式来描述数字系统硬件的结构和行为的语言,用它可以表示逻辑电路图、逻辑表达式。
- 2022-03-04 02:46:20下载
- 积分:1
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mdio
用VIVADO软件编写的,实现以太网芯片88E1510中的mdio控制模块代码,并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)
- 2020-09-16 14:37:55下载
- 积分:1
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adv7511_hdmi
FPGA与HDMI ADV7511接口源代码(FPGA HDMI Adv7511 interface)
- 2020-10-08 14:37:36下载
- 积分:1