MAX2839 SPI寄存器

基于verilog的LZS压缩和解压算法，压缩比1；2 。里面带有C原言的代码。已经通过验证！(Verilog based LZS compression and decompression algorithm, compression ratio 1; 2. It has the C code in it. It has been verified!)

《CPLDFPGA嵌入式应用开发技术白金手册》源代码，涉及FPGA/CPLD的各个方面，键盘扫描，LED扫描等简单程序及滤波器等的设计(" CPLDFPGA platinum embedded application development technology handbook" source code, related to FPGA/CPLD all aspects of the keyboard scanning, LED scanning filters, such as simple procedures and design)

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)

基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)

高速32位吠陀乘数使用吠陀数学设计。这有一个比其他类型的乘法器，非常少的延迟。

SAA7113 ＦＰＧＡ开发实例，非常经典(The SAA7113 FPGA development examples, very classic)

这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)