基于DDS的DA正弦波输出

LatticeECP3 SERDES/PCS 使用指南(LatticeECP3 SERDES/PCS usage guide)

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当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter

说明：  there's a clock divider for DE2 altra board clock (50MHz)

说明：  artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)

用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder

this a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.-this is a spartan 3E base project file. this is the project of game in which vga is interfaced to FPGA. this file is main file in which vga timing is maintained.

用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)

des code source vhdl sur fpga

C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)