自己写得一个关于sine（32X24）的程序

这个程序VHDL计数器计数二进制数并显示脉冲易于程序计数器的VHDL，我们需要了解逻辑电路的VHDL语言的程序员

VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA

说明：  基于FPGA，用verilog hdl语言实现串口收发实验(Based on FPGA, using Verilog HDL language to achieve serial port transceiver experiment)

说明：  数字下变频verilog实现，项目中常用模块(apply the digital down frequency in my project)

小家电常用芯片HT66F0185的UART 使用例子，已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)

本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

isa总线接口，可以实现与isa总线　的IO和MEMERY接口(isa bus interface can be achieved with the isa bus IO interfaces and MEMERY)

Digital Design and Modeling with VHDL and Synthesis

基于Matlab的FPGA数字半带滤波器设计(Matlab-based FPGA digital half-band filter design)