系统的 Verilog 设计与验证示例

A programming language that can decode alpha numeric

32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)

片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)

本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)

Link the VGA adapter located in the altera DE2board to a monitor

LatticeECP3 SERDES/PCS 使用指南(LatticeECP3 SERDES/PCS usage guide)

vivado工程下的Verilog语言的CRC_16,并行输入任意字节长度，均可求出来，数据的校验码，代码给的是512个字节宽度的数据源，长度可以自行修改，亲测实际工程~~~

用于生成adams或recurdyn所需的路面不平度，用于悬架或其他的仿真(Adams or recurdyn used to generate the required road roughness for suspension or other simulation)

适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)

VHDL实现简单打地鼠游戏机，北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)