自适应fir滤波器verilog代码及仿真波形

带DDR3内存条，HDMI，PCIE，SD，usb，i2c,spi,uart接口

说明：  fpga的hdmi驱动，只包括视频信号没使用音频线，总体跟DVI控制一样，可参考DVI说明手册进行观看(driver of HDMI using fpga)

单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)

说明：  该设计使用8个AXI视频直接存储器访问（AXI VDMA）引擎同时移动16个流（8个传输视频流和8个接收视频流），每个流以1920 x 1080像素格式以60赫兹刷新率移动，每个像素24个数据位。此设计还具有额外的视频等效AXI流量，该流量由为1080p视频模式配置的四个LogiCORE AXI流量发生器（ATG）核心生成。ATG核心根据其配置生成连续的AXI流量。在本设计中，ATG被配置成以1080p模式生成AXI4视频流量。这使得系统吞吐量需求达到DDR的80%左右带宽。每个AXI VDMA由LogiCORE IP测试模式生成器（AXI TPG）核心驱动。AXI VDMA配置为在自由运行模式下运行。每个AXI VDMA读取的数据被发送到能够将多个视频流多路复用或叠加到单个输出视频流的通用视频屏幕显示（AXI OSD）核心。AXI OSD核心的输出驱动板载高清媒体接口（HDMI技术）视频显示接口通过RGB到YCrCb颜色空间转换器核心和逻辑核心IP色度重采集器核心。LogiCore视频定时控制器（AXI VTC）生成所需的定时信号。(The design uses eight AXI video direct memory access (AXI VDMA) engines to simultaneously move 16 streams (eight transmit video streams and eight receive video streams), each in 1920 x 1080 pixel format at 60 Hz refresh rate, and 24 data bits per pixel. This design also has additional video equivalent AXI traffic generated from four LogiCORE AXI Traffic Generator(ATG) cores configured for 1080p video mode. The ATG core generates continuous AXI traffic based on its configuration. In this design, ATG is configured to generate AXI4 video traffic in 1080p mode. This pushes the system throughput requirement to approximately 80% of DDR bandwidth. Each AXI VDMA is driven from a LogiCORE IP Test Pattern Generator (AXI TPG)core. AXI VDMA is configured to operate in free running mode. Data read by each AXI VDMA is sent to a common Video On-Screen Display (AXI OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream.)

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)

按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

详细讲述TURBO码的FPGA实现原理，可作参考，不是码源(A detailed account of the FPGA implementation of principle of the TURBO code can be used as reference, not source code)

基于CPLD硬件描述语言编写的五电平SVPWM脉冲触发程序(Five level SVPWM pulse trigger program based on CPLD hardware description language)