VHDL digital system design and engineering practice 4, including the principles,...

VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)

HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看(HDB3_verilog coding procedures)

fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。-fpga CAN Bus Controller source, each with explanatory documents on the use of methods.

这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充(This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded)

60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))

有自己制作的下载器原理图，包含了stlinkv2,XDS100V3,USBBLASTER.原理图和封装，一款多功能下载器。(Have their own production downloader schematic diagram, contains stlinkv2, XDS100V3, USBBLASTER. Schematic diagram and encapsulation, a multi-function downloader.)

Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

加法器（使用verilog编写的）,虽然简单，但是这也是学习verilog最基础的东西！希望大家一起学习！-The accumulator (uses the verilog compilation), although it is simple, but this also is studies most foundation of the verilog! Hopes everybody studies together!