sd卡中读取数据

lite pcie 的程序，参考demo可以用来熟悉pcie axi-lite方式

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

此代码是一个状态机（西班牙）对FPGA nexys3 7段显示器显示一个4个字母。该代码是verilog语言进行

dds叫数字频率合成计，是一种在FPGA广泛使用的信号生成方式，根据频率可控，比一般的信号优点很多。

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

若农场路无车辆，则在高速路保持绿灯。在探测农场路有车辆，高速路上的交通灯应由绿到黄，再到红，并允许农场路方向灯变绿，绿灯亮一段时间，由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)

通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)

利用matlab设计了一个切比雪夫滤波器，并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance. )

modelsim下的60进制计数器源码和测试激励文件(modelsim M counter 60 under the source file and test incentives)

基于FPGA硬件平台的数字显示时钟系统，通过数码管能够实时地显示系统或自定义时间。