FIFO design

FPGA开发全攻略，工程师创新宝典，由张国斌等书写-FPGA development

xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise

用于编码器计数，速度能够达到5ms/1圈，速度很快，而且杂波也很好，能够准确应用。已应用在工程中很多年

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)

不错的verilog学习语言资料，详细地对verilog语言中的重要语句应用进行分析。(A good the verilog learn language information, verilog language statement application.)

RGB 与YCbCr 颜色空间可以相互转化(RGB and YCbCr color space can be transformed into each other)

本程序是锁相环的仿真程序，具有接收端载波同步的功能。注释详尽，程序规范。发端的调制方式有单载波调制，BPSK调制，QPSK调制可供选择。程序中有星座图，锁相环的频差、相差图，以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)

cordic算法，实现加减乘除、幂次方、开方的运算(CORDIC algorithm implementation, power add, subtract, multiply and divide and square root operations)

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )

用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)