FIFO design

FPGA 控制MPU6050陀螺仪传感器，通过串口把数据打印出来(FPGA controls the MPU6050 gyroscope sensor and prints out the data through the serial port)

设计了一基于现场可编程门阵列（FPGA）的低频数字式相位测量仪。该测量仪包括数字式移相信号发生器和相位测量仪两部分，分别完成移相信号的发生及其频率、相位差的预置及数字显示、发生信号的移相以及移相后信号相位差和频率的测量与显示几个功能。其中数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；相位测量仪能测量移相信号的频率、相位差的测量和显示。两个部分均采用基于FPGA的数字技术实现，使得该系统具有抗干扰能力强, 可靠性好等优点。()

说明：  基于fpga的spi通信测试 可与stm32进行spi通信测试(SPI communication test based on FPGA can test SPI communication with stm32)

。给出了时域滤波的基本原理以及通常采用的 IIR 椭圆地物杂波滤波器的设计方法。重点研究了回归滤波器这一时域滤波算 法。从正交多项式的拟合出发，给出了回归滤波器抑制地物杂波的基本原理及 其滤波实现过程。通过对回归滤波器的计算复杂度的研究，寻找使回归滤波器 计算量最小的正交多项式。分析了回归滤波器频率响应特性，比较了回归滤波 器与IIR 椭圆地物杂波滤波器的计算复杂度。利用仿真的雷达信号，分析了回 归滤波器的地物杂波抑制性能。回归滤波器实际上是一高通滤波器，它在滤掉 低频地物杂波的同时，对落在滤波器阻带内的天气回波信号同样会造成衰减。 在天气回波信号谱宽固定的情况下，通过改变天气回波信号的平均多普勒频率， 分析了回归滤波器对它的衰减情况。在基于一组实际采集的雷达信号的基础上， 给出了回归滤波器的地物杂波抑制比随着滤波器阶数的变化情况。(Firstly, this dissertation introduces the research background and significance of ground clutter suppression, analyzes the characteristics of the ground clutter and weather signals in the Doppler weather radars and simulates Doppler radar echo signals (It includes ground clutter, weather echo signals and the mixture of them). The simulated signals are used later to study the time and frequency domain ground clutter suppression. Secondly, this dissertation talks about the time domain filtering, gives the basic theory of time domain filtering and describes the design method of the usually used fifth-order elliptic infinite impulse response (IIR) ground clutter filter. In the time domain, the work focuses on the regression filter. From the orthogonal polynomials fit, this dissertation gives the basic theory of the regression filter for ground clutter suppression and the filtering process using a regression filter. Through the study of the computational complexity of regression)

根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend

UART program for fun(UART)

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)

cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system

使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为-10DB-CDMA system using MATLAB to complete the relevant receivers, which Hadamard matrix of 128 bands, simulation-10DB-bit signal to noise ratio for