FIFO design

《Verilog HDL 程序设计教程》9-"Verilog HDL Design Guide" 9

csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)

spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

AD转换的Matlab程序，将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率)，然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)

基于FPGA设计的电子密码锁是一个小型的数字系统，与普通机械锁相比，具有许多独特的优点：保密性好，防盗性强，可以不用钥匙，记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages：good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)

ebook verilog HDL programming book

-- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn

TR0114 VHDL Language Reference

图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像基本操作,几何变换,直方图,灰度化处理等(System Generator based image processing engineering, multimedia processing FPGA implementation source code, the basic operation of the image, geometric transformations, histogram, gray processing)