FIFO design

alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.

说明：  Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.

这是一个数字逻辑课程的电子表的实现，利用VHDL语言实现，初学者可以完全掌握，很有帮助。(This is the realization of the electronic timepiece a digital logic course, the use of VHDL language, beginners can fully grasp and helpful.)

利用FPGA来采集美新加速度计的数据，并将FPGA采集到的数据传给ARM系统处理-The use of FPGA to collect the new U.S. accelerometer data and the data collected FPGA passed ARM system processing

内容太短。注意请： 代码没有很好的描述将被删除，你不会得到任何点。请描述一下更好地获得更多积分。

如何编写测试文件，，test bench的编写方法和是列，，总结的非常好的东西(how to code test bench in verilog)

A program for a simple multiplexer using modelsimSE6.3

运用matlab实现fft变换，用于地震资料频谱分析！(FFT transform)

基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using

密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)