过滤多相

采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化(VHDL hardware description language using the dual-caliber RAM block memory initialization)

Verilog语言编写的电话计费系统，这只是源代码，需要在quartusII等软件下运用-Verilog language telephone billing system, this is only the source code, the need to use software such as quartusII

credit base network on chip(network on chip (noc))

WM8731芯片的音效处理verilog代码， WM8731芯片是音频ADCDAC芯片(WM8731 audio processing chip verilog code, WM8731 chip audio ADC DAC chip)

说明：  LTE is an abbreviation for Long Term Evolution.

VerilogHDL.自动增益控制模块中产生控制电压的部分-VerilogHDL. Automatic Gain Control Module have some control voltage

一种基于FPGA的CPU设计-FPGA-based CPU design ........

使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为-10DB-CDMA system using MATLAB to complete the relevant receivers, which Hadamard matrix of 128 bands, simulation-10DB-bit signal to noise ratio for

这是一个HDB3编码器，可以将普通的二进制序列转化为符合HDB3编码规则的双极性序列-This is a HDB3 encoder, can be transformed into an ordinary binary sequences in order to comply with the rules of HDB3 bipolar coding sequence

说明：  16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)